1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a conductive layer of small conductive resistance.
2. Description of the Prior Art
Among semiconductor devices, nonvolatile semiconductor memory devices losing no data in power-off states are widely employed in general. An EEPROM (electrically erasable and programmable read only memory) which can freely program data and is capable of electrically writing and erasing information is known as one of such nonvolatile semiconductor memory devices.
In relation to such an EEPROM, known is a flash memory having memory cells each formed by a single transistor, which can electrically batch-erase information charges written therein.
FIG. 34 is a sectional view showing a conventional flash memory. Referring to FIG. 34, a source region 113 and drain regions 102 are formed on a surface of a silicon substrate 101 at distances from each other. Floating gate electrodes 104 are formed on the silicon substrate 101 through gate oxide films 103. Control gate electrodes 106 consisting of doped polysilicon layers 106a and tungsten silicide layers 106b are formed on the floating gate electrodes 104 through interlayer isolation films 105. Side wall oxide films 107 are formed on side walls of the control gate electrodes 106 and the floating gate electrodes 104. A silicon oxide film 115 is formed on the silicon substrate 101, to cover the control gate electrodes 106.
When gate electrodes are refined, conductive resistance thereof is disadvantageously increased in general. Known is a method of preventing this problem by forming wiring layers on the gate electrodes and connecting the former with the latter thereby reducing conductive resistance.
FIG. 35 is a sectional view showing wiring layers 294 formed on conventional gate electrodes 292. Referring to FIG. 35, the gate electrodes 292 consisting of doped polysilicon layers 292a and tungsten silicide layers 292b are formed on a silicon substrate 201 through gate oxide films 291. A silicon oxide film 293 is formed to cover the gate electrodes 292. The wiring layers 294 of aluminum are formed on the silicon oxide film 293 in a width substantially identical to that of the gate electrode 292. The wiring layers 294 are electrically connected with the gate electrodes 292 respectively.
In this structure, the sectional areas of conductive layers are not reduced following refinement of the gate electrodes 292, due to the presence of the wiring layers 294. Consequently, increase of the conductive resistance can be prevented.
When the conventional flash memory shown in FIG. 34 is further refined, the sectional area of the source region 113 is reduced. Thus, the conductive resistance of the source region 113 is increased, to retard the operating speed of the flash memory. Further, a leakage current is readily generated. In order to solve this problem, a wiring layer of aluminum or the like may be formed on the silicon oxide film 115, to be electrically connected with the source region 113. In this method, however, the wiring layer formed on the silicon oxide film 115 causes a step, to result in a problem such as difference in depth of focus in a subsequent photolithographic step, for example.
When the conventional semiconductor device shown in FIG. 35 is further refined, on the other hand, the sectional areas of the wiring layers 294 are reduced to increase the conductive resistance. The wiring layers 294 may be increased in height, in order to increase the sectional areas. In this case, however, it is so difficult to pattern the wiring layers 294 in prescribed shapes that adjacent ones of the wiring layers 294 readily come into contact with each other. Consequently, the yield of the semiconductor device is disadvantageously reduced.